A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.
The text treats testing and testability as integral parts of the digital design process rather than afterthoughts.
Gate-level faults, fault collapsing, and structural modeling in Verilog. Digital System Test and Testable Design: Using ...
Random and deterministic test generation methods, plus sequential circuit test generation.
Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in A distinguishing feature is the extensive use of
The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered
Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs. Courses Syllabus – Monsoon 2024 - pgadmissions@iiit
Memory fault models, MBIST (Memory BIST) methods, and functional procedures.